Zero-latency network on chip (NoC)

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United States of America Patent

PATENT NO 9882839
SERIAL NO

14720947

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Abstract

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Packet format configurability is extended for packets transported on physical links of an Intellectual Property (IP) core interconnect by using at least two independent parameters: one parameter governing data-width and one parameter governing latency penalty. The at least two independent parameters allow creation of transport protocol packets without additional latency insertion, which is useful for low-latency applications. The at least two independent parameters also allow creation of narrow packets with multi-cycle additional latency, which is useful for latency tolerant, area sensitive applications.

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Patent Owner(s)

  • QUALCOMM INCORPORATED;QUALCOMM TECHNOLOGIES, INC.

International Classification(s)

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Boucard, Philippe Le Chesnay, FR 43 454
Lecler, Jean-Jacques Antibes, FR 32 377

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