Packed two source inter-element shift merge processors, methods, systems, and instructions
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United States of America Patent
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Sep 13, 2016
Grant Date -
Sep 17, 2015
app pub date -
Mar 13, 2014
filing date -
Mar 13, 2014
priority date (Note) -
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Abstract
A processor includes a decoder to receive an instruction that indicates first and second source packed data operands and at least one shift count. An execution unit is operable, in response to the instruction, to store a result packed data operand. Each result data element includes a first least significant bit (LSB) portion of a first data element of a corresponding pair of data elements in a most significant bit (MSB) portion, and a second MSB portion of a second data element of the corresponding pair in a LSB portion. One of the first LSB portion of the first data element and the second MSB portion of the second data element has a corresponding shift count number of bits. The other has a number of bits equal to a size of a data element of the first source packed data minus the corresponding shift count.
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