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Abstract

A semiconductor device including a semiconductor substrate having an active region and an element isolation region; memory-cell transistors and select-gate transistors each formed above the substrate and having a gate electrode formed above the active region via a first insulating film, the gate electrode including a floating gate electrode, an interelectrode insulating film, and a control gate electrode; the element isolation region being formed of a trench and an insulating film filled in the trench, a position of an upper surface of the insulating film located between the gate electrodes of the memory cell transistors being higher than a position of the upper surface of the floating gate electrode, and a position of an upper surface of the insulating film located between the gate electrodes of the select-gate transistors being lower than a position of the upper surface of the floating gate electrode.

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First Claim