PARALLEL MULTIPLEX TEST SYSTEM AND METHOD

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United States of America Patent

APP PUB NO 20150268294A1
SERIAL NO

14263072

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Abstract

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A parallel multiplex test system is disclosed. The parallel multiplex test system is used for testing N devices under test (DUTs) in the N isolation boxes via N test signals through N test channels. The parallel multiplex test system comprises a central processing unit and N function-test modules, wherein N is a positive integer greater than one. The parallel multiplex test system requests the function-test modules to take the function-tests for N DUTs according to the test items which have not been tested, so that different function-tests are taken for all of the DUTs simultaneously through different channels.

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Patent Owner(s)

Patent OwnerAddress
LITE-ON TECHNOLOGY CORPORATION22F NO 392 RUEY KUANG ROAD NEIHU DIST TAIPEI CITY
LITE-ON ELECTRONICS (GUANGZHOU) LIMITEDNO 25 GUANGPU W RD GUANGZHOU SCIENCE CITY GUANGZHOU HI-TECH INDUSTRIAL DEVELOPMENT ZONE GUANGZHOU

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
CHENG, KO-YUNG NEW TAIPEI CITY, TW 1 1
CHIANG, TZUNG-NAN NEW TAIPEI CITY, TW 2 5
FU, HSIEN-CHIEH NEW TAIPEI CITY, TW 1 1
LIEN, SHENG-HSIEN NEW TAIPEI CITY, TW 1 1
SONG, XI-XIANG DONGGUAN CITY, GUANGDONG, CN 1 1

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