Selecting a low power state based on cache flush latency determination

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United States of America Patent

PATENT NO 9665153
SERIAL NO

14221696

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Abstract

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In an embodiment, a processor includes a plurality of cores to independently execute instructions, a shared cache coupled to the cores and including a plurality of lines to store data, and a power controller including a low power control logic to calculate a flush latency to flush the shared cache based on a state of the plurality of lines. Other embodiments are described and claimed.

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Patent Owner(s)

  • INTEL CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Chakki, Samudyatha Austin, US 3 19
Choubal, Ashish V Austin, US 30 493
Durg, Ajaya V Austin, US 14 139
Mandhani, Arvind San Francisco, US 34 354
Muthukumar, Kalyan Bangalore, IN 22 310
Raman, Arvind Austin, US 29 382
Ramani, Sundar Bangalore, IN 6 30

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