System and method for computer memory with linked paths
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United States of America Patent
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Nov 22, 2016
Grant Date -
Sep 24, 2015
app pub date -
Apr 7, 2014
filing date -
Mar 20, 2014
priority date (Note) -
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Abstract
A first memory buffer has a first high speed memory channel and a second high speed memory channel. A second memory buffer is connected to the first memory buffer through a first connection. The second memory buffer has a third high speed memory channel and a fourth high speed memory channel. The first connection connects the first high speed memory channel and the third high speed memory channel. A first memory controller is connected to the first memory buffer through the second high speed memory channel. A second memory controller is connected to the second memory buffer through a second connection. The second connection is connected to the second memory buffer through the fourth high speed memory channel. A first memory module set is connected to the first memory buffer and a second memory module set is connected to the second memory buffer.
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