Configuration memory storing data by injecting carriers in gate insulating layer of MISFET
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United States of America Patent
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Dec 27, 2016
Grant Date -
Sep 24, 2015
app pub date -
Mar 18, 2015
filing date -
Mar 20, 2014
priority date (Note) -
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Abstract
A configuration memory includes: memory cell including first and second MISFETs, each of the first and second MISFETs having a gate insulating layer, a source, a drain, and a gate, one of the source and the drain of the first MISFET being connected to a first bit line, the gate of the first MISFET being connected to a first word line, one of the source and the drain of the second MISFET being connected to a second bit line, the gate of the second MISFET being connected to the first word line; a sense amplifier having an output terminal and connected to the first and second bit lines; and a control circuit which is configured to write data in the memory cell by injecting carriers in the gate insulating layer of the first MISFET.
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