Method to form dual channel group III-V and Si/Ge FINFET CMOS and integrated circuit fabricated using the method
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United States of America Patent
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Dec 6, 2016
Grant Date -
Sep 24, 2015
app pub date -
Jun 9, 2015
filing date -
Feb 11, 2014
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Abstract
A method includes providing a structure having a substrate, a first insulating layer on the substrate, a first semiconductor material layer on the first insulating layer, a second insulating layer on the first semiconductor layer in a first portion of the structure and a second semiconductor layer of a second, different semiconductor material on the second insulating layer in the first portion. The method further includes growing additional first semiconductor material on the first semiconductor layer in a second portion of the structure forming a regrown semiconductor layer; forming first fins in the regrown semiconductor layer and second fins in the second semiconductor layer; and forming gate structures upon the first and second fins. A height difference, relative to a surface of the first insulating layer, of the gate structures formed upon the first fins and the gate structures formed upon the second fins is less than a predetermined value.
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