Stressed nanowire stack for field effect transistor

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United States of America Patent

PATENT NO 9287358
APP PUB NO 20150270340A1
SERIAL NO

14221349

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Abstract

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A disposable gate structure is formed over the alternating stack of first semiconductor material portions and second semiconductor material portions. The second semiconductor material portions are removed selective to the first semiconductor material portions to form suspended semiconductor nanowires. Isolated gate structures are formed in regions underlying the disposable gate structure by deposition and recessing of a first gate dielectric layer and a first gate conductor layer. After formation of a gate spacer, source regions, and drain regions, raised source and drain regions are formed on the source regions and the drain regions by selective deposition of a semiconductor material. The disposable gate structure is replaced with a replacement gate structure by deposition and patterning of a second gate dielectric layer and a second gate conductor layer. Distortion of the suspended semiconductor nanowires is prevented by the disposable gate structure and the isolated gate structures.

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Patent Owner(s)

  • INTERNATIONAL BUSINESS MACHINES CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Frank, Martin M Dobbs Ferry, US 125 1460
Hashemi, Pouya White Plains, US 600 4483
Khakifirooz, Ali Mountain View, US 842 11906
Reznicek, Alexander Troy, US 1407 11211

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