Dielectric liner for a self-aligned contact via structure
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United States of America Patent
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Jun 7, 2016
Grant Date -
Sep 24, 2015
app pub date -
Oct 9, 2014
filing date -
Mar 24, 2014
priority date (Note) -
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Abstract
At least one dielectric material layer having a top surface above the topmost surface of the gate electrode of a field effect transistor is formed. Active region contact via structures are formed through the at least one dielectric material layer to the source region and the drain region. A self-aligned gate contact cavity is formed over the gate electrode such that at least one sidewall of the gate contact cavity is a sidewall of the active region contact via structures. A dielectric spacer is formed at the periphery of the gate contact cavity by deposition of a dielectric liner and an anisotropic etch. A conductive material is deposited in the gate contact cavity and planarized to form a self-aligned gate contact via structure that is electrically isolated from the active region contact via structures by the dielectric spacer.
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