Importance

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Abstract

A logical gate circuit (5) and four stages of flip flips (4a-4d) are assigned to each pixel (1). A controller (7) inputs four phase identification signals into the logical gate circuit (5) and also inputs a start signal STR into a shift register (4) synchronously with the four mutually different phases defined by the phase identification signals. During one round of scanning all the pixels (1) for a readout control, if an enable signal ENBL is set to “0” while an output of a phase identification circuit (110) is “1”, a charge accumulation time at the pixel (1) concerned becomes equal to a readout period T. If the enable signal ENBL is set to “1” while the output of the phase identification circuit (110) is “1”, electric charges accumulated in a photodiode (11) until that point are entirely discarded, so that the charge accumulation time becomes shorter than the readout period T. Thus, the charge accumulation time at each pixel (1) can be controlled to ensure an adequate SN ratio while avoiding signal saturation at some pixels even if the light source has a bright line at a specific wavelength.

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First Claim