WORD LINE DECODERS FOR DUAL RAIL STATIC RANDOM ACCESS MEMORIES
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United States of America Patent
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Issued Date -
Oct 22, 2015
app pub date -
Apr 22, 2014
filing date -
Apr 22, 2014
priority date (Note) -
Abandoned
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Abstract
Word line decoders for dual rail SRAM devices are disclosed for high performance sub-micron SRAM designs. One embodiment is an SRAM device that includes a memory cell array and a word line traversing the memory cell array for selecting memory cells of the memory cell array. A row decode-driver coupled to the word line toggles the word line between logic levels of a memory cell supply based on select signals that toggle between logic levels of a peripheral supply. The row decoder-driver toggles the word line without utilizing level shifters along the word line access path.
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