Configurable Test Address And Data Generation For Multimode Memory Built-In Self-Testing
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
N/A
Issued Date -
N/A
app pub date -
Sep 10, 2014
filing date -
Apr 25, 2014
priority date (Note) -
Abandoned
status (Latency Note)
Importance
Abstract
In certain embodiment, built-in self-test (BIST) circuitry for multiport memory comprises a configurable address generator and a configurable data generator. The configurable address generator can be configured to concurrently generate first and second logical memory addresses corresponding to physically neighboring first and second memory cells of the multiport memory for any selected memory mode of a plurality of available memory modes having different column-multiplexing schemes. The configurable data generator can be configured to concurrently generate two sets of data for the selected memory mode, such that (i) the first set of data is written into and read from the multiport memory via a first memory port using the first logical memory address and (ii) the second set of data is written into and read from the multiport memory via a second memory port using the second logical memory address. The BIST circuitry enables efficient, physically aware built-in self-testing.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully