Semiconductor device including gate channel having adjusted threshold voltage

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United States of America Patent

PATENT NO 9275908
APP PUB NO 20150318218A1
SERIAL NO

14729105

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Abstract

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A semiconductor device includes at least one first semiconductor fin formed on an nFET region of a semiconductor device and at least one second semiconductor fin formed on a pFET region. The at least one first semiconductor fin has an nFET channel region interposed between a pair of nFET source/drain regions. The at least one second semiconductor fin has a pFET channel region interposed between a pair of pFET source/drain regions. The an epitaxial liner is formed on only the pFET channel region of the at least one second semiconductor fin such that a first threshold voltage of the nFET channel region is different than a second threshold voltage of the pFET channel.

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Patent Owner(s)

  • INTERNATIONAL BUSINESS MACHINES CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Kerber, Pranita Mount Kisco, US 101 710
Ouyang, Qiqing C Yorktown Heights, US 60 1098
Reznicek, Alexander Troy, US 1406 11120

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