Utilizing a distributed and parallel set of neurosynaptic core circuits for neuronal computation and non-neuronal computation
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United States of America Patent
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May 12, 2020
Grant Date -
Nov 12, 2015
app pub date -
May 8, 2014
filing date -
May 8, 2014
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Abstract
Embodiments of the invention provide a neurosynaptic system comprising a delay unit for receiving and buffering axonal inputs, and a neural computation unit for generating neuronal outputs by performing a set of computations based on at least one axonal input received by the delay unit. The system further comprises a permutation unit for receiving external inputs to the system, and transmitting external outputs from the system. The permutation unit maps each external input received as either an axonal input to the delay unit or an external output from the system. The permutation unit maps each neuronal output generated by the neural computation unit as either an axonal input to the delay unit or an external output from the system. The neural computation unit comprises multiple electronic neurons, multiple electronic axons, and a plurality of electronic synapse devices interconnecting the neurons with the axons.
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