Chip with programmable shelf life
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United States of America Patent
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Jan 26, 2016
Grant Date -
Nov 12, 2015
app pub date -
May 6, 2014
filing date -
May 6, 2014
priority date (Note) -
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Abstract
A method includes forming a first interconnect structure and a second interconnect structure each located within an interlevel dielectric (ILD). A first top metal layer and a second top metal layer are formed disposed on and in direct electrical connection with the first interconnect. Similarly, a third top metal layer and a fourth top metal layer are formed disposed on and in direct electrical connection with the second interconnect. A silicon layer is deposited above the first, second, third and fourth top metal layers in direct contact with the first and fourth top metal layers and separated from each of the second and third top metal layers by a barrier layer. The silicon layer is exposed to an oxygen-containing environment to form a silicon dioxide layer.
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