Managing memory transactions in a distributed shared memory system supporting caching above a point of coherency
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United States of America Patent
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Aug 30, 2016
Grant Date -
Nov 19, 2015
app pub date -
Jun 23, 2014
filing date -
May 15, 2014
priority date (Note) -
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Abstract
In response to execution in a memory transaction of a transactional load instruction that speculatively binds to a value held in a store-through upper level cache, a processor core sets a flag, transmits a transactional load operation to a store-in lower level cache that tracks a target cache line address of a target cache line containing the value, monitors, during a core TM tracking interval, the target cache line address for invalidation messages from the store-in lower level cache until the store-in lower level cache signals that the store-in lower level cache has assumed responsibility for tracking the target cache line address, and responsive to receipt during the core TM tracking interval of an invalidation message indicating presence of a conflicting snooped operation, resets the flag. At termination of the memory transaction, the processor core fails the memory transaction responsive to the flag being reset.
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