Memory cell having built-in read and write assist
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United States of America Patent
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May 24, 2016
Grant Date -
Nov 19, 2015
app pub date -
May 16, 2014
filing date -
May 16, 2014
priority date (Note) -
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Abstract
A memory cell having integrated read and write assist functionality includes a storage element and first and second switching circuits. The first switching circuit is configured to selectively couple a first internal storage node of the storage element with a first bit line. The second switching circuit is configured to selectively couple a second internal storage node of the storage element with a second bit line. During a read operation, at least one of the first and second switching circuits is configured to increase a switching threshold of at least one inverter in the storage element. During a write operation, at least one of the first and second switching circuits is configured such that ground bounce associated with at least one of the first and second switching circuits assists in writing a logical state of the memory cell.
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