Semiconductor memory device capable of reducing chip size
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United States of America Patent
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Apr 25, 2017
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app pub date -
Jul 29, 2015
filing date -
Jul 17, 2009
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Abstract
According to one embodiment, a first well of the first conductivity type which is formed in a substrate. a second well of a second conductivity type which is formed in the first well. The plurality of memory cells, the plurality of first bit line select transistors, and the plurality of second bit line select transistors are formed in the second well, and the plurality of first bit line select transistors and the plurality of second bit line select transistors are arranged on a side of the sense amplifier with respect to the plurality of memory cells of the plurality of bit lines.
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