Importance

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Abstract

Embodiments of the present invention relate to an architecture that extends counter life by provisioning each counter for an average case and handles overflow via an overflow FIFO and an interrupt to a process monitoring the counters. This architecture addresses a general optimization problem, which can be stated as, given N counters, for a certain CPU read interval T, of how to minimize the number of storage bits needed to store and operate these N counters. Equivalently, this general optimization problem can also be stated as, given N counters and a certain amount of storage bits, of how to optimize and increase CPU read interval T. This architecture extends the counter CPU read interval linearly with depth of the overflow FIFO.

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First Claim