TRIGGER DETECTION FOR POST CONFIGURATION TESTING OF PROGRAMMABLE LOGIC DEVICES

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United States of America Patent

APP PUB NO 20150370672A1
SERIAL NO

14313443

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Abstract

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Various techniques are provided to determine signal values of a programmable logic device (PLD) prior to the running of an external test application. In one example, a machine-implemented method includes monitoring, by a PLD, a signal of the PLD. The method also includes detecting a trigger condition associated with the signal. The method also includes storing data in memory of the PLD corresponding to values of the signal. The method also includes passing the stored data from the PLD to an external device running a test application. The stored data comprises values of the signal occurring before the running of the test application.

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Patent Owner(s)

Patent OwnerAddress
LATTICE SEMICONDUCTOR CORPORATION111 SW 5TH AVENUE SUITE 700 PORTLAND OR 97204

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Caslis, Brian Wilsonville, US 1 1
Lenka, Pradeep Milpitas, US 3 5
Lin, Andrew San Jose, US 81 1881

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