Microelectronic package with consolidated chip structures

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 9355996
APP PUB NO 20150371968A1
SERIAL NO

14837561

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Abstract

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A chip package has multiple chips that may be arranged side-by-side or in a staggered, stair step arrangement. The contacts of the chips are connected to interconnect pads carried on the chips themselves or on a redistribution substrate. The interconnect pads desirably are arranged in a relatively narrow interconnect zone, such that the interconnect pads can be readily wire-bonded or otherwise connected to a package substrate.

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Patent Owner(s)

Patent OwnerAddress
INVENSAS CORPORATION3025 ORCHARD PARKWAY SAN JOSE CA 95134

International Classification(s)

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Crisp, Richard Dewitt Hornitos, US 113 2738
Haba, Belgacem Saratoga, US 718 20815
Mohammed, Ilyas San Jose, US 305 7578
Zohni, Wael San Jose, US 152 2939

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