LOW LEAKAGE ANALOG SWITCH
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United States of America Patent
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Issued Date -
Dec 31, 2015
app pub date -
Nov 26, 2014
filing date -
Jun 25, 2014
priority date (Note) -
Abandoned
status (Latency Note)
Importance
Abstract
A semiconductor isolating switch has two series connected primary field effect transistors (FET), a first one the primary FETs is coupled between a first node and an intermediate node, and a second one of the primary FETs is coupled between the intermediate node and a second node. A controllable pull-up FET is coupled in series to a controllable pull-down FET. The controllable pull-up FET is coupled between a power rail node and a common node and the controllable pull-down FET is coupled between the common node and a ground rail node. A leakage control transistor is coupled between the common node and the intermediate node. The gates of all of the transistors are coupled to a switch control node.
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