Method and apparatus for selecting an interconnect frequency in a computing system
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United States of America Patent
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Nov 7, 2017
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app pub date -
Jul 23, 2014
filing date -
Jul 23, 2014
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Abstract
In an embodiment, a processor includes at least one core and an interconnect that couples the at least one core and the cache memory. The interconnect is to operate at an interconnect frequency (fCL). The processor also includes a power management unit (PMU) including fCL logic to determine whether to adjust the fCL responsive to a Bayesian prediction value that is associated with scalability of a workload to be processed by the processor. The Bayesian prediction value may be determined based on one or more activity measures associated with the processor. Other embodiments are described and claimed.
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