CLOCK TO OUT PATH OPTIMIZATION

United States of America Patent

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N/A
Issued Date
Jan 28, 2016
app pub date
Jul 23, 2014
filing date
Jul 23, 2014

priority date (Note)
Abandoned

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Abstract

A place and route technique is provided for a programmable logic device to optimize a delay difference between a clock to out path and a clock out path.

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Patent Owner(s)

Patent Owner	Address
LATTICE SEMICONDUCTOR CORPORATION	5555 NE MOORE CT HILLSBORO OR 97124

International Classification(s)

G06F:ELECTRIC DIGITAL DATA PROCESSING

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[Patents Count]

Inventor(s)

Inventor Name	Address	# of filed Patents	Total Citations
Sun, Richard	Los Gatos, US	6	9
Yi, Yanhua	Cupertino, US	9	24
Zhao, Jun	Fremont, US	511	11937

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CLOCK TO OUT PATH OPTIMIZATION

Number of patents in Portfolio can not be more than 2000

United States of America Patent

14339164

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14339164

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