SYSTEMS AND/OR METHODS FOR LEVERAGING IN-MEMORY STORAGE IN CONNECTION WITH THE SHUFFLE PHASE OF MAPREDUCE

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United States of America Patent

APP PUB NO 20160034205A1
SERIAL NO

14449517

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Abstract

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Certain example embodiments relate to a computer system for performing a map reduce sequence. Nodes therein include at least one processor and memory and are divided into at least mapper and reducer nodes. Each mapper node executes a map function on input to generate intermediate output elements. Each said intermediate output element includes a first key-value pair. Each element key includes associated map and reduce task identifiers. Each element value includes substantive data, organized as another key-value pair. The intermediate output elements are stored to memory. Each reducer node: retrieves at least intermediate output element values from the memory of a given mapper node, using specified map and reduce task identifiers; stores the retrieved element values to its memory; executes a reduce function on the retrieved element values, in order; and outputs a result from the reduce function for the map reduce sequence. Disk operations advantageously are reduced or eliminated.

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Patent Owner(s)

Patent OwnerAddress
SOFTWARE AG USA INC11700 PLAZA AMERICA DRIVE RESTON VA 20190

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
DEVGAN, Manish Herndon, US 36 1115
MEHRA, Gagan Oakland, US 4 68

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