Decoder and method for decoding an encoded sequence of bits

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United States of America Patent

PATENT NO 9419656
APP PUB NO 20160036465A1
SERIAL NO

14445146

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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A decoder including an input, a branch metric unit, a path metric unit, a starting state unit, and a tail path forcing unit, or alternatively, a state consistency unit. The input is configured to receive a encoded sequence of bits. The branch metric unit is configured to determine a plurality of branch metrics for a plurality of respective transitions between a plurality of states in a trellis representation of a code used to generate the encoded sequence of bits. The path metric unit is configured to determine, based on the plurality of branch metrics, path metrics corresponding to a plurality of maximum likelihood survival paths reaching the plurality of respective states in the trellis representation. The starting state unit is configured to store a plurality of starting states for the respective maximum likelihood survival paths. The tail path forcing unit is configured to select a tail path of a maximum likelihood survival path at a w number of states prior to this maximum likelihood survival path's ending state in the trellis representation to result in this maximum likelihood survival path's stored starting and ending states being the same, wherein w is equal to a constraint length of the decoder minus one. The state consistency unit is configured to determine whether a maximum likelihood survival path has an ending state in the trellis representation that is equivalent to its stored starting state, wherein if the state consistency unit's determination is positive, the branch metric unit and path metric unit are configured to end the determinations of the branch and path metrics.

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Patent Owner(s)

  • INTEL IP CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Kuo, Chun-Hsuan San Diego, US 50 172

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