Adaptive error correction in a memory system
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United States of America Patent
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Nov 15, 2016
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app pub date -
Jul 30, 2014
filing date -
Jul 30, 2014
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Abstract
According to one aspect, a method for adaptive error correction in a memory system includes reading data from a memory array of a non-volatile memory device in the memory system. Error correcting logic checks the data for at least one error condition stored in the memory array. Based on determining that the at least one error condition exists, a write-back indicator is asserted by the error correcting logic to request correction of the at least one error condition. Based on determining that the at least one error condition does not exist, accesses of the memory array continue without asserting the write-back indicator.
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