METHOD FOR MANUFACTURING A FLOATING GATE MEMORY ELEMENT

Number of patents in Portfolio can not be more than 2000

United States of America Patent

APP PUB NO 20160043096A1
SERIAL NO

14820459

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Abstract

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The disclosed technology generally relates to fabricating semiconductor devices and more particularly to fabricating a floating-gate based memory device. In one aspect, a method of fabricating a memory device comprises forming a stack of horizontal layers comprising alternating sacrificial layers of a first type and sacrificial layers of a second type; forming a vertical opening through the horizontal stack of layers; forming a first vertical dielectric layer on a sidewall of the vertical opening; forming a vertical floating gate layer on the first vertical dielectric layer; forming a second vertical dielectric layer on the vertical floating gate layer; filling the vertical opening with a channel material; forming cavities of a first type by removing the sacrificial layers of the second type to expose the first vertical dielectric layer; removing portions of the first vertical dielectric layer and the vertical floating gate layer at locations adjacent to the cavities of the first type, such that portions of the second vertical dielectric layer are exposed; filling the cavities of the first type with an isolating material; forming cavities of a second type by removing the sacrificial layers of the first type, wherein the cavities of the second type exposes portions of the first vertical dielectric layer; forming a third dielectric layer in the cavities of the second type, wherein the third dielectric layer is formed on the first vertical dielectric layer; and forming a conductive material in the cavities of the second type.

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Patent Owner(s)

Patent OwnerAddress
IMEC VZWKAPELDREEF 75 LEUVEN 3001

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Blomme, Pieter Leuven, BE 15 80

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