ACTIVITY CORRELATION BASED OPTIMAL CLUSTERING FOR CLOCK GATING FOR ULTRA-LOW POWER VLSI
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United States of America Patent
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Issued Date -
Feb 18, 2016
app pub date -
Aug 17, 2015
filing date -
Aug 15, 2014
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Abandoned
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Abstract
A clustering bus-specific clock gating method is described to reduce the dynamic power consumed by redundant clock ticks in gate-level. The method exploits correlations between flip-flops for clock gating. An activity correlation matrix is introduced to describe the correlations between the flip-flops. Based on activity correlation information, the flip-flops are classified into several clusters. A payoff function is also described to find an optimal classification scheme. Based on the classification strategy, flip-flop clusters that are less active and more correlated will be gated.
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