LOW POWER SRAM
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United States of America Patent
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Issued Date -
Mar 3, 2016
app pub date -
Sep 2, 2015
filing date -
Sep 2, 2014
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
A static random access memory (SRAM) that includes an array of storage cells arranged as rows and columns and a read controller to manage reading from the storage cells. The array of storage cells includes word lines that correspond to the rows and bit lines that correspond to the columns. The read controller is configured to identify consecutive reads from storage cells accessed via a same one of the word lines and precharge the bit lines no more than once during the consecutive reads.
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