Multi-chip silicon substrate-less chip packaging
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United States of America Patent
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Nov 5, 2019
Grant Date -
Mar 3, 2016
app pub date -
Aug 26, 2014
filing date -
Aug 26, 2014
priority date (Note) -
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Abstract
Examples generally provide a stacked silicon interconnect product and method of manufacture. The stacked silicon interconnect product includes a silicon substrate-less interposer comprising a plurality of metallization layers, wherein at least one metallization layer includes a plurality of metal segments separated by dielectric material. The stacked silicon interconnect product also includes a first die coupled to a first side of the silicon substrate-less interposer via a first plurality of microbumps. The stacked silicon interconnect product further includes a second die coupled to a second side of the silicon substrate-less interposer via a second plurality of microbumps, the second die communicatively coupled to the first die through a metallization layer of the plurality of metallization layers.
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