Time-division multiplexing data aggregation over high speed serializer/deserializer lane

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United States of America Patent

PATENT NO 10027600
APP PUB NO 20160072605A1
SERIAL NO

14482295

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Abstract

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A digital signal interface includes a multiplexer coupled to receive a plurality of data signals from at least one of a microprocessor, a microcontroller, or a field-programmable gate array (FPGA), the multiplexer multiplexing the plurality of data signals. The interface further includes a serializer/deserializer (SerDes) transceiver coupled to receive the multiplexed data signals, the SerDes transceiver serializing the multiplexed data signals and transmitting the serialized data signals.

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Patent Owner(s)

Patent OwnerAddress
SMART EMBEDDED COMPUTING INC2900 SOUTH DIABLO WAY SUITE 190 TEMPE AS 85282

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Hofer, Reinhold Olching, DE 3 6
Jacht, Armin Munich, DE 2 6
Kruecker, Stephan Unterhaching, DE 1 2

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