Method for fabricating a carrier-less silicon interposer
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United States of America Patent
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Jan 15, 2019
Grant Date -
Mar 17, 2016
app pub date -
Nov 24, 2015
filing date -
Feb 25, 2013
priority date (Note) -
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Abstract
An insulating second element is provided and overlies a surface of a first element which consists essentially of a material having a CTE of less than 10 ppm/° C. and has a first thickness in a first direction normal to the surface. Openings extend in the first direction through the second element. The first element is abraded to produce a thinned first element having a second thickness less than the first thickness. Conductive elements are formed at a first side of the interposer coincident with or adjacent to a surface of the thinned first element remote from the second element. A conductive structure extends through the openings in the second element, wherein the conductive elements are electrically connected with terminals of the interposer through the conductive structure, and the terminals are disposed at a second side of the interposer opposite from the first side.
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