Coalescing adjacent gather/scatter operations
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United States of America Patent
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May 9, 2017
Grant Date -
Apr 14, 2016
app pub date -
Dec 18, 2015
filing date -
Dec 26, 2012
priority date (Note) -
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status (Latency Note)
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Abstract
According to one embodiment, a processor includes an instruction decoder to decode a first instruction to gather data elements from memory, the first instruction having a first operand specifying a first storage location and a second operand specifying a first memory address storing a plurality of data elements. The processor further includes an execution unit coupled to the instruction decoder, in response to the first instruction, to read contiguous a first and a second of the data elements from a memory location based on the first memory address indicated by the second operand, and to store the first data element in a first entry of the first storage location and a second data element in a second entry of a second storage location corresponding to the first entry of the first storage location.
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