Clock buffers with pulse drive capability for power efficiency
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United States of America Patent
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Feb 14, 2017
Grant Date -
Apr 14, 2016
app pub date -
Dec 17, 2015
filing date -
Jun 13, 2014
priority date (Note) -
In Force
status (Latency Note)
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Abstract
A clock driver is provided. The clock driver includes a multi-stage delay cell having an input, a positive pulse driving branch, a negative pulse driving branch, and an output. The input is for receiving an original version of a reference clock signal input to the clock driver and used to generate a global clock signal. The output is connected to the positive pulse driving branch and the negative pulse driving branch. The clock driver further includes a pulse generator having positive and negative pulse generator portions respectively connected to outputs of the positive and negative pulse driving branches. The pulse generator generates, at any given time, one of a positive pulse and a negative pulse responsive to a positive pulse enable signal and a negative pulse enable signal, respectively, and the original version of the reference clock signal input to the clock driver without modification.
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