Lowering parasitic capacitance of replacement metal gate processes
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United States of America Patent
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Jun 20, 2017
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N/A
app pub date -
Dec 30, 2015
filing date -
Mar 5, 2014
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Abstract
The present disclosure provides a method of forming a gate structure of a semiconductor device with reduced gate-contact parasitic capacitance. In a replacement gate scheme, a high-k gate dielectric layer is deposited on a bottom surface and sidewalls of a gate cavity. A metal cap layer and a sacrificial cap layer are deposited sequentially over the high-k gate dielectric layer to form a material stack. After ion implantation in vertical portions of the sacrificial cap layer, at least part of the vertical portions of the material stack is removed. The subsequent removal of a remaining portion of the sacrificial cap layer provides a gate component structure. The vertical portions of the gate component structure do not extend to a top of the gate cavity, thereby significantly reducing gate-contact parasitic capacitance.
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