Interlevel conductor pre-fill utilizing selective barrier deposition

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United States of America Patent

PATENT NO 9583386
SERIAL NO

14874307

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Abstract

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A substrate is provided having a dual damascene structure formed within a dielectric material over the substrate. The dual damascene structure includes a trench and an opening formed to extend from a bottom of the trench to an underlying conductive material, with the underlying conductive material exposed at a bottom of the opening. The dual damascene structure is exposed to a sealing process by which the exposed surfaces of the dielectric material in the opening are sealed without covering the underlying conductive material exposed at the bottom of the opening. The sealing process can be one or more of deposition of a flowable film, deposition of an amorphous carbon barrier layer, and formation of a self-assembled monolayer of an amino group. After the sealing process, an electroless deposition process is performed to fill the opening with a metallic material in a bottom-to-top manner up to the bottom of the trench.

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Patent Owner(s)

  • LAM RESEARCH CORPORATION

International Classification(s)

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Ashtiani, Kaihan San Jose, US 19 1706
Dordi, Yezdi Palo Alto, US 117 2663
Kolics, Artur Dublin, US 74 1318
Lee, William T Dublin, US 17 621
Nalla, Praveen Fremont, US 15 82
Van, Cleemput Patrick A San Jose, US 52 3483
Wong, Derek San Jose, US 18 46
Zhao, Larry Lake Oswego, US 31 608

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