Level Shifter With Low Static Power Dissipation

Number of patents in Portfolio can not be more than 2000

United States of America Patent

APP PUB NO 20160118987A1
SERIAL NO

14525240

Stats

ATTORNEY / AGENT: (SPONSORED)

Importance

Loading Importance Indicators... loading....

Abstract

See full text

In one embodiment, a level shifter has a cascade voltage-switching logic (CVSL) structure having two pull-up networks connected in a positive feedback arrangement, each pull-up network connected in series with a corresponding pull-down network. The effective transistor sizes of the two pull-up networks are different such that, at power on, if a level-shifter node connected to an output inverter initially has an in-between voltage level (e.g., at or near the midpoint between the output voltage-domain power-supply voltage and ground), the node voltage will quickly be driven either high or low (depending on the level-shifter design and other initial conditions), thereby reducing leakage current through the output inverter that could otherwise be maintained if the pull-up networks had the same effective transistor size. In addition, one of the pull-down networks has an additional pull-down transistor to accelerate node-voltage driving away from the midpoint to ensure proper operation of the level shifter.

Loading the Abstract Image... loading....

First Claim

See full text

Family

Loading Family data... loading....

Patent Owner(s)

Patent OwnerAddress
LATTICE SEMICONDUCTOR CORPORATION5555 NE MOORE CT HILLSBORO OR 97124

International Classification(s)

  • [Classification Symbol]
  • [Patents Count]

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Ho, Vinh Milpitas, US 9 9
Yao, Jianguo Fremont, US 34 105
Zhou, Yaqing Santa Clara, US 1 1

Cited Art Landscape

Load Citation

Patent Citation Ranking

Forward Cite Landscape

Load Citation