Enhancement mode inverter with variable thickness dielectric stack
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United States of America Patent
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Jun 14, 2016
Grant Date -
May 5, 2016
app pub date -
Oct 29, 2014
filing date -
Oct 29, 2014
priority date (Note) -
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Abstract
An enhancement-mode inverter includes a load transistor and a drive transistor. The load transistor has a bottom gate architecture with a first source, a first drain, a load channel region, a first semiconductor layer, and a first gate electrode. A load gate dielectric is in the load channel region, and has a load dielectric thickness. The drive transistor has a bottom gate architecture with a second source, a second drain, a drive channel region, a second semiconductor layer, and a second gate electrode. A drive gate dielectric is in the drive channel region, and has a drive dielectric thickness less than the load dielectric thickness. The first source is electrically connected to the second drain and the first gate is electrically connected to the first drain. The load gate dielectric and the drive gate dielectric are part of a common shared dielectric stack.
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