STATIC RANDOM ACCESS MEMORY FREE FROM WRITE DISTURB AND TESTING METHOD THEREOF
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United States of America Patent
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Issued Date -
May 19, 2016
app pub date -
Nov 18, 2014
filing date -
Nov 18, 2014
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
A static random access memory (SRAM) includes a memory cell array, a row decoder, a plurality of word-line drivers and an arbiter. The memory cell array includes a plurality of memory cell rows, wherein the memory cell rows are enabled by a plurality of word-lines, respectively. The row decoder is arranged to assert one of the memory cell rows according to a row address. The plurality of word-line drivers are each coupled to the row decoder and one of the memory cell rows. The arbiter is arranged to prevent multiple memory cells at a same word-line from being accessed at a same time.
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