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United States of America Patent
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May 19, 2016
app pub date -
Nov 12, 2015
filing date -
Nov 19, 2014
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Abstract
A P-channel type MOSFET and an N-channel type MOSFET formed by a CMOS process are connected in series. A high-voltage signal and a low-voltage signal are applied to the drain of one of transistors. Prescribed bias voltage is applied to both gates in order that only a low-voltage signal can pass through both conduction paths.
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