Driver output with dynamic switching bias
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United States of America Patent
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Jul 26, 2016
Grant Date -
May 19, 2016
app pub date -
Nov 14, 2014
filing date -
Nov 14, 2014
priority date (Note) -
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status (Latency Note)
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Abstract
A circuit of an output stage of a push-pull driver having dynamic biasing may include a stacked configuration of field effect transistors (PFETs) having a first PFET, a second PFET, and a third PFET, whereby the first PFET is connected to a first supply voltage, the third PFET is connected to an output of a switchable voltage bias generator circuit, and the second PFET is electrically connected between the first PFET and the third PFET. A transmission gate may be connected to a second supply voltage, whereby the transmission gate electrically connects the second supply voltage to an electrical connection between the first PFET and the second PFET based on a first operating state for preventing a voltage breakdown condition associated with the stacked configuration of PFETs. The third PFET is bias controlled via the switching of the output of the switchable voltage bias generator circuit.
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