Importance

Loading Importance Indicators...

Abstract

A processor arranges a first dummy pattern in each of a plurality of circuit blocks of a first layer included in hierarchical design data of a semiconductor device; sets an arrangement candidate region as a candidate for arranging a second dummy pattern in a region, which is located between a circuit block boundary and the first dummy pattern and in which the first dummy pattern is not arranged, in each of the plurality of circuit blocks; arranges the plurality of circuit blocks in an upper-layer region of a second layer higher than the first layer; and arranges the second dummy pattern in a portion formed by joining a first arrangement candidate region of a first circuit block and a second arrangement candidate region of a second circuit block, which contact each other, among the arrangement candidate regions of the plurality of circuit blocks arranged in the upper-layer region.

Loading the Abstract Image...

First Claim