ASYMMETRIC ULTRATHIN SOI MOS TRANSISTOR STRUCTURE AND METHOD OF MANUFACTURING SAME

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United States of America Patent

APP PUB NO 20160155844A1
SERIAL NO

14904711

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Abstract

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A method for manufacturing an asymmetric super-thin SOIMOS transistor is disclosed. The method comprises: a. providing a substrate composed of an insulating layer (200) and a semiconductor layer (300); b. forming a gate stack (304) on the substrate; c. removing semiconductor materials of the semiconductor layer (300) on a source region side to form a first vacancy (001); d. removing insulating materials of the insulating layer (200) in the source region and under channel near the source region to form a second vacancy (002); e. filling semiconductor materials into the first vacancy (001) and the second vacancy (002) to connect with the semiconductor materials above the second vacancy (002); and f. performing source/drain implantation. Compared with the prior art, the method of the disclosure can suppress the short channel effects and enhance device performance.

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Patent Owner(s)

Patent OwnerAddress
INSTITUTE OF MICROELECTRONICS CHINESE ACADEMY OF SCIENCES100029 BEIJING CITY CHAOYANG DISTRICT BEITUCHENG WEST ROAD NO 3 CHINESE ACADEMY OF SCIENCES INSTITUTE OF MICROELECTRONICS MUNICIPAL DISTRICT BEIJING CITY 100029

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
YIN, Haizhou Poughkeepsie, US 241 2072
ZHANG, Keke Shandong, CN 13 53

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