Method of forming performance optimized gate structures by silicidizing lowered source and drain regions
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United States of America Patent
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Sep 27, 2016
Grant Date -
Jun 9, 2016
app pub date -
Dec 5, 2014
filing date -
Dec 5, 2014
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Abstract
A performance optimized CMOS FET structure and methods of manufacture are disclosed. The method includes forming source and drain regions for a first type device and a second type device. The method further includes lowering the source and drain regions for the first type device, while protecting the source and drain regions for the second type device. The method further includes performing silicide processes to form silicide regions on the lowered source and drain regions for the first type device and the source and drain regions for the second type device.
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