Minimization of bias temperature instability (BTI) degradation in circuits

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United States of America Patent

PATENT NO 9859873
SERIAL NO

14560109

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Abstract

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A circuit structure is provided. The circuit structure includes first pfet device. The circuit structure further includes a first nfet device connected to the pfet device. The circuit structure further includes a keeper nfet device that reduces stress associated with the first nfet device by keeping the first nfet device off during its functional state. The circuit structure further includes a keeper pfet device that reduces stress associated with the first pfet device by keeping the first pfet device off during its functional state.

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Patent Owner(s)

  • INTERNATIONAL BUSINESS MACHINES CORPORATION

International Classification(s)

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Agarwal, Navin Kolkata, IN 12 39
Arsovski, Igor Williston, US 117 1327
Bringivijayaraghavan, Venkatraghavan Tamilnadu, IN 61 595
Rengarajan, Krishnan S Bangalore, IN 31 259

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