Buffer access for side-channel attack resistance

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United States of America Patent

PATENT NO 10747907
APP PUB NO 20160171252A1
SERIAL NO

14955269

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Abstract

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A cryptographic accelerator (processor) retrieves data blocks for processing from a memory. These data blocks arrive and are stored in an input buffer in the order they were stored in memory (or other known order)—typically sequentially according to memory address (i.e., in-order.) The processor waits until a certain number of data blocks are available in the input buffer and then randomly selects blocks from the input buffer for processing. This randomizes the processing order of the data blocks. The processing order of data blocks may be randomized within sets of data blocks associated with a single read transaction, or across sets of data blocks associated with multiple read transactions.

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Patent Owner(s)

Patent OwnerAddress
CRYPTOGRAPHY RESEARCH INC4453 NORTH FIRST STREET SUITE 100 SAN JOSE CA 95134

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Leiserson, Andrew John San Francisco, US 22 368
Marson, Mark Evan Lafayette, US 35 81

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