FinFET with epitaxial source and drain regions and dielectric isolated channel region
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United States of America Patent
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Apr 11, 2017
Grant Date -
Jun 16, 2016
app pub date -
Feb 22, 2016
filing date -
May 1, 2014
priority date (Note) -
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Abstract
A semiconductor device is provided that includes a pedestal of an insulating material present over at least one layer of a semiconductor material, and at least one fin structure in contact with the pedestal of the insulating material. Source and drain region structures are present on opposing sides of the at least one fin structure. At least one of the source and drain region structures includes at least two epitaxial material layers. A first epitaxial material layer is in contact with the at least one layer of semiconductor material. A second epitaxial material layer is in contact with the at least one fin structure. The first epitaxial material layer is separated from the at least one fin structure by the second epitaxial material layer. A gate structure present on the at least one fin structure.
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