Compiler method for generating instructions for vector operations on a multi-endian processor
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United States of America Patent
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Mar 7, 2017
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app pub date -
Dec 19, 2014
filing date -
Dec 19, 2014
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Abstract
A compiler includes a vector instruction processing mechanism that generates instructions for vector instructions in a way that assures correct operation in a bi-endian environment, wherein the processor architecture contains instructions with an inherent endian bias. The compiler uses a code generation endian preference that is specified by the user, and that determines a natural element order. When the compiler processes a computer program, it generates instructions for vector operations by determining whether the vector instruction has an endian bias that matches the specified endian preference (i.e., the inherent element order of the vector instruction matches the natural element order). When the vector instruction has no endian bias, or when the endian bias of the vector instruction matches the specified endian preference, the compiler generates one or more instructions for the vector instruction as it normally does. When the endian bias of the vector instruction does not match the specified endian preference, the compiler generates instructions to fix the mismatch.
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